The present invention relates to a flash memory device and a method of increasing the speed of the erasing operation.
The flash memory device maintains data stored therein even when the power is not being supplied, i.e. the flash memory device is a type of nonvolatile memory device. This flash memory device is divided into a NOR flash memory device and a NAND flash memory device in accordance with the pattern of memory cell array included therein. The operation of the flash memory device is divided into a program operation, an erasing operation and a read operation.
A memory cell array in the NAND flash memory device includes a plurality of blocks, and each of the blocks has strings connected to a plurality of bit lines. Here, the string includes a drain select transistor connected to the bit line, a plurality of memory cells and a source select transistor connected to a common source line. Since this cell array in the NAND flash memory device is well-known, further description concerning the cell array will be omitted.
The erasing operation of the NAND flash memory device is performed in units of block. That is, all flash memory cells included in a block are erased during an erase operation. When several blocks need to be erased, the address of a first block to be erased is inputted, and then the first block is erased. The address of a second block next to the first block is inputted after the first block has been erased, so that the second block may be erased.
In brief, the address corresponding to a specific block always needs to be inputted to erase that block according to the conventional erase technique. In other words, when erasing N (integer above 2) blocks, all N addresses need to be inputted.